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hv_to_5v_tpsm365r6

Block orb_weaver_tpsm365r6_fixed:tpsm365r6_fixed_5v placed in / of mouse-joystick-pcb. High-voltage input to a fixed 5 V or 3.3 V rail: TI TPSM365R6V5 or V3 600 mA buck module, one family source with the regulator part and the second output capacitor as the variant

Lifecycle routed
Family tpsm365r6_fixed 5v (buck): 5 V (TPSM365R6V5, two 22 uF output capacitors)
Placement anchor (-21.25, -7) mm, rotation 90°, front side; anchor rule: inferred (block not in the anchor table): the footprint with most pads
Sheet hv_to_5v_tpsm365r6.kicad_sch; sheet pins: the library's arrangement
Drawing mouse-joystick-pcb-hv_to_5v_tpsm365r6.svg

On the Board

hv_to_5v_tpsm365r6 on the board

Block 6 of the board view: 7.5 × 19.8 mm on the top side, its centre 22.7 mm left of and 8.2 mm above the board centre (X right, Y up, as the enclosure tables); 9 footprints. The picture is the top render clipped around the block, the rectangle the extent of its footprints' courtyards.

Description

High-voltage input to a regulated 5 V (TPSM365R6V5, two 22 uF output capacitors) step-down supply: TI TPSM365R6V5RDNR fixed-output 600 mA buck module, FB tied to VOUT, MODE/SYNC tied to VCC (forced PWM), PGOOD pulled up to VOUT through 10k. Ports VIN, VOUT, PGOOD, GND. Output voltage and capacitor ratings judged from the datasheet facts at publication (release.json); hardware validation pending. BUCK profile. VIN 3.6 V to 65 V (facts, recommended operating); the block's input capacitors are 100 V 1206 parts and its VIN copper is block-local (PWR_HV_LOCAL), so the board's power entry carries its own class. 600 mA output; the module integrates the inductor; VCC bypass and the 100 nF high-frequency input bypass are the block's. PGOOD is the module's open-drain window-comparator output (rising at about 107 %, falling at about 94 % of the set point); the block pulls it up as its description says. Fixed variants: FB is tied to VOUT and pin 11 is MODE/SYNC, tied to VCC in this block (forced PWM); PGOOD is pulled up to the block's own output, so its high level is VOUT

Ports

The brief's shape, edge, class and meaning for each port, then what the board wires it to.

Port Shape Edge Class Wired to Board net Board class GPIO Meaning On this board
GND passive west PWR_RETURN_LOCAL GND /GND PWR_RETURN_LOCAL Return for the module (pin 10) and every input and output capacitor.
PGOOD output west Default PG_5V /PG_5V Default Open-drain power good, pulled up to VOUT by R13001 (10 k); high level is VOUT.
VIN passive west PWR_HV_LOCAL +36V_SW /+36V_SW PWR_HV_BUS 3.6 to 65 V input on VIN (pin 3) and EN (pin 2, tied: always enabled).
VOUT passive west PWR_5V_LOCAL +5V_SW /+5V_SW PWR_5V Fixed 5 V or 3.3 V output by variant, 600 mA; FB/BIAS (pin 9) tied here.

Parts

As placed on the board's sheet; 9 of 9 paired with the brief's references by symbol identity, the rest given the brief's role where the internal part has one, else the catalog's role slug; the placement is the Placement field of the board's symbol, else of the library's (D38); the manufacturer part and the LCSC number are the board's BOM's.

Reference Brief Part Value Role Placement Manufacturer part LCSC DNP
C1701 C13001 OW-PASS-1206B105K101NT 1uF cin_a beside U1701.2 (EN), on VIN 1206B105K101NT C91151
C1702 C13002 OW-PASS-1206B105K101NT 1uF cin_b beside U1701.3 (VIN), on VIN 1206B105K101NT C91151
C1703 C13003 OW-PASS-1206B105K101NT 1uF cin_c beside U1701.2 (EN), on VIN 1206B105K101NT C91151
C1704 C13004 OW-PASS-GRM188R72A104KA35D 100nF cin_hf beside U1701.3 (VIN), on VIN GRM188R72A104KA35D C77058
C1705 C13005 OW-PASS-0805B105K250NT 1uF cvcc beside U1701.8 (VCC), on VCC 0805B105K250NT C89190
C1706 C13006 OW-PASS-1206X226M100NT 22uF cout_a beside U1701.4 (VOUT), on VOUT 1206X226M100NT C108717
C1707 C13007 OW-PASS-1206X226M100NT 22uF cout_b beside U1701.9 (BIAS), on VOUT 1206X226M100NT C108717
R1701 R13001 OW-RES-10K-0402 10k pgood_pullup beside U1701.1 (PGOOD), on PGOOD ERJ2GEJ103X C278577
U1701 U13001 OW-PWR-TPSM365R6V5RDNR TPSM365R6V5RDNR regulator TPSM365R6V5RDNR C19078014

Operating Notes

  • Signal path: VIN (3.6 to 65 V after start-up, UVLO rising 3.4 V typical) enters VIN (pin 3) and EN (pin 2, tied to VIN, so the module runs whenever input is present); the integrated-inductor module delivers VOUT (pin 4), 600 mA maximum; FB/BIAS (pin 9) is tied to VOUT for the fixed output; GND is pin 10.
  • Variants (family.json): 5v fits U13001 = OW-PWR-TPSM365R6V5RDNR with both 22 uF output capacitors; 3v3 fits OW-PWR-TPSM365R6V3RDNR and leaves C13007 unpopulated. One schematic and one copper; the publisher writes each variant's part and DNP into its block and judges the output voltage and capacitor ratings from the facts (release.json). Output accuracy is +/-1.5 % in forced PWM (5 V facts).
  • MODE/SYNC (pin 11) is tied to VCC (the internal LDO output, pin 8, bypassed by C13005 1 uF), which selects forced PWM. BOOT (pin 7) is left open and the two SW pins (5, 6) are tied only to each other, as the block was drawn and built: the module integrates its inductor and nothing external connects there.
  • PGOOD (pin 1) is the module's open-drain window comparator: high once VOUT is inside the window (rising at about 107 %, falling at about 94 % of the set point, 25 us deglitch, about 2 ms delay after regulation), pulled up to VOUT by R13001 (10 k), so its high level is the output voltage itself (5 V or 3.3 V) and a 3.3 V host reads the 5 V variant's PGOOD only through a 5 V-tolerant input.
  • Bypass: three 1 uF 100 V 1206 capacitors (C13001 to C13003) and a 100 nF 0603 (C13004) at VIN; the 22 uF output capacitors sit at about 50 % (5 V) and 33 % (3.3 V) of their rating, inside the family's 0.6 planning fraction. Current limits from the facts: high-side short-circuit 1 A typical, low-side 0.7 A typical.
  • The placing board provides the VIN entry on its own class (the block's PWR_HV_LOCAL copper is block-local), a load of at most 600 mA, its own name for the VOUT net (the port is VOUT because the variant sets the voltage) and the thermal path: RthJA 56.3 C/W on a JEDEC 4-layer board, so give the module's pad a ground pour and vias.

Placement and Routing

Buck module and output capacitors

U13001, C13006, C13007, C13001, C13002, C13003, C13004, C13005, R13001

U13001 converts VIN to the fixed VOUT; C13006 and C13007 (22 uF) hold the output. C13007 is unpopulated on the 3v3 variant. Three 1 uF 100 V capacitors and a 100 nF high-frequency bypass across VIN to GND at the module's input. C13005 (1 uF) bypasses the internal LDO output VCC (pin 8), which also sets MODE/SYNC to forced PWM. R13001 (10 k) pulls the open-drain PGOOD (pin 1) up to VOUT.

  • Place: Place C13006 and C13007 at VOUT (pin 4) with their GND ends at pin 10; keep the output loop short and on one layer.
  • Place: Place C13004 (100 nF) closest to VIN (pin 3) and GND (pin 10), the 1 uF parts beside it; the input current loop is the noisiest on the block.
  • Place: Place C13005 at pin 8 with a short return to pin 10.
  • Place: Anywhere between VOUT and the PGOOD port; a low-current node.
  • Route: VOUT is block-local copper (PWR_5V_LOCAL); the board names and classes the net on its side of the sheet pin.
  • Route: Wide, short VIN copper from the capacitors into pin 3; no via between C13004 and the module if the layer allows it.
  • Route: VCC stays inside the block; nothing else loads it.
  • Route: PGOOD is a logic flag on the Default class; its high level equals VOUT.

Library Identity

Block orb_weaver_tpsm365r6_fixed:tpsm365r6_fixed_5v
Resolution the placed id is in the library
Brief design_block_families/tpsm365r6_fixed/source/tpsm365r6_fixed.brief.yaml, the family's brief
Published sheet 8d37d1931ee9bd3c
Published PCB 17ea37099656e93f
Family release tpsm365r6_fixed variant 5v, profile buck; 5 V (TPSM365R6V5, two 22 uF output capacitors); geometry 70b435f451caf109; copper 5ef3613b97b53de7; hardware unvalidated; qualification matches
Placed sheet fd15f021ac746a0a: matches the brief: its 9 parts by internal part, every port by name and shape; the file is the board's copy under its own designators
Netlist check ok on 2026-10-15: every pin on the brief's net; 10 identity records differ, the board's own instances