inputs¶
Subsystem sheet /inputs of camera-gpio-interface-pcb, from the board recipe subsystems/inputs.subsystem.yaml.
The two pyControl BNC inputs, TRIG IN and SYNC IN: each jack into the shared USBLC6 ESD clamp referenced to +5V, then the logic_input_2ch_5v_schmitt_sn74lvc2g17 block, which conditions a 3.3 V or 5 V edge into clean 3.3 V logic (TRIG_IN, SYNC_IN) and taps each for the InstrumentPort; a 680 Ω activity LED on each conditioned output.
Board note: board-authored sheet, 7 parts
Notes¶
- J301 is TRIG IN (the 150 Hz frame trigger, to the cameras' Line 3) and J302 is SYNC IN (the Rsync pulse, to Line 0 and to SYNC OUT). Both chains are identical, so reversing the roles is a cable swap plus the cameras' TriggerSource. Shells to ground, no termination footprint.
- U301 (USBLC6-2P6) clamps TRIG_RAW and SYNC_RAW with its VBUS on +5V, so it sits above a 5 V logic high and never conducts on a 3.3 V signal. The block behind it (4.7 kΩ series, 470 pF to ground, 100 kΩ pull-down on the jack side) tolerates a 5 V source or a ±5 V OneBox DAC plugged in by mistake, and an unplugged jack reads low, so the cameras receive nothing rather than noise.
- D301 and D302 through R301 and R302 (680 Ω, about 1.8 mA) show activity on TRIG_IN and SYNC_IN: a 25 ms Rsync pulse once a second blinks, the 150 Hz trigger reads half-lit. The instrument taps TRIG_IN_INST and SYNC_IN_INST are the block's own IN_A_INST and IN_B_INST ports, so the board adds none.
- The conditioning delays a 3.3 V edge about 2 µs, the same on both inputs, so trigger-to-Rsync timing is preserved. TRIG_IN then feeds the three Line 3 drivers and SYNC_IN the three Line 0 drivers and the SYNC OUT driver, through the root.
Ports¶
The recipe's ports as the sheet symbol carries them, the root label each meets, and the net's class, MCU pin and meaning.
| Port | Shape | Wired to | Net | Class | GPIO | Meaning | |
|---|---|---|---|---|---|---|---|
+3.3V |
passive | shared | +3.3V |
/+3.3V |
PWR_3V3_NARROW | The only logic rail, from the TPS73733 on the power sheet; always on while USB is present, as the InstrumentPort block requires | |
+5V |
passive | shared | +5V |
/+5V |
PWR_5V_NARROW | VBUS after the USB block's Schottky (+5V_USB in the design record): the Line 0 pull-ups and every ESD array's clamp reference | |
GND |
passive | shared | GND |
/GND |
PWR_RETURN_LOCAL | Board ground; every BNC shell and camera pins 5 and 6 | |
SYNC_IN |
output | SYNC_IN |
/SYNC_IN |
Default | Conditioned Rsync from the SYNC IN BNC, 3.3 V, to the three Line 0 drivers and the SYNC OUT driver | ||
SYNC_IN_INST |
output | SYNC_IN_INST |
/SYNC_IN_INST |
INSTRUMENT | DIG1: the conditioned Rsync after the Schmitt (the input block's IN_B_INST) | ||
TRIG_IN |
output | TRIG_IN |
/TRIG_IN |
Default | Conditioned 150 Hz frame trigger from the TRIG IN BNC, 3.3 V, to the three camera channels' Line 3 drivers | ||
TRIG_IN_INST |
output | TRIG_IN_INST |
/TRIG_IN_INST |
INSTRUMENT | DIG0: the conditioned trigger after the Schmitt (the input block's IN_A_INST) |
Blocks¶
The recipe's roles and the placements that fill them on this board.
| Role | Instance | Block | Lifecycle | Summary |
|---|---|---|---|---|
logic_input_2ch_5v_schmitt_sn74lvc2g17 |
logic_input_2ch_5v_schmitt_sn74lvc2g17 |
orb_weaver_private:logic_input_2ch_5v_schmitt_sn74lvc2g17 |
routed | Two-channel single-ended logic input conditioner: per-channel series/RC filtering plus an SN74LVC2G17 dual Schmitt-trigger buffer that turns a 3.3 V or 5 V field-wired logic signal into clean 3.3 V logic, with a 100 ohm InstrumentPort tap on each output. |
Glue¶
The subsystem's own parts and nets, drawn by the board around the blocks.
| References | Part | Value | Role |
|---|---|---|---|
D301, D302 |
OW-MISC-APHHS1005CGCK |
APHHS1005CGCK | activity LEDs on TRIG_IN (D301) and SYNC_IN (D302) |
J301, J302 |
OW-CONN-HL-BNC-KHDA |
HL-BNC-KHDA | the input BNC jacks: J301 TRIG IN, J302 SYNC IN; shells to ground |
R301, R302 |
OW-PASS-RC0402FR-07680RL |
680 | LED series resistors, about 1.8 mA |
U301 |
OW-MISC-USBLC6-2P6 |
USBLC6-2P6 | ESD clamp across both raw inputs, VBUS on +5V |
| Net | Kind | Pins | Meaning |
|---|---|---|---|
+5V |
port | U301.5 |
the clamp's reference: above a 5 V logic high, so it never conducts on a signal |
GND |
port | D301.1, D302.1, J301.2, J302.2, U301.2 |
jack shells, the clamp's return, the LED cathodes |
SYNC_IN |
port | R302.1 |
conditioned Rsync, 3.3 V, out to the root (the LED hangs on it) |
TRIG_IN |
port | R301.1 |
conditioned 150 Hz trigger, 3.3 V, out to the root (the LED hangs on it) |
SYNC_RAW |
label | J302.1, U301.3, U301.4 |
the SYNC IN jack to the clamp and the block's IN_B_RAW |
TRIG_RAW |
label | J301.1, U301.1, U301.6 |
the TRIG IN jack to the clamp and the block's IN_A_RAW |
| wire | D301.2, R301.2 |
the TRIG IN LED's anode node | |
| wire | D302.2, R302.2 |
the SYNC IN LED's anode node |